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CY28317-2
FTG for Mobile VIATM PL133T and PLE133T Chipsets
1CY28317-2
Features
* Single-chip system frequency synthesizer for mobile VIA PL133T and PLE133T chipsets * Programmable clock output frequency with less than 1 MHz increment * Integrated fail-safe Watchdog Timer for system recovery * Automatic switch to HW-selected or SW-programmed clock frequency when Watchdog Timer time-out occurs * System RESET generation capability after a Watchdog Timer time-out occurs or a change in output frequency via SMBus interface * Support SMBus byte Read/Write and block Read/ Write operations to simplify system BIOS development * Vendor ID and Revision ID support * Programmable drive strength for SDRAM and PCI output clocks * Programmable output skew for CPU, PCI and SDRAM * Maximized EMI Suppression using Cypress's Spread Spectrum technology * Available in 48-pin SSOP and TSSOP packages
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps PCI to PCI Output Skew: ............................................ 500 ps
Block Diagram
VDD_REF REF0 X1 X2 XTAL OSC
PLL Ref Freq
Pin Configuration[1]
GND_CPU *FS2/REF1 REF0
VTT_PWRGD#
REF1/FS2*
MULT_SEL IREF VTT_PWRGD# PCI_STOP# CPU_STOP# PD#
PLL 1
/2,3,4
CPU0:1, CPUT, CPUC
VDD_PCI PCI0_F/FS4* PCI1/FS3* PCI2:6
SDATA SCLK
SMBus Logic
Reset Logic
PLL2
/2
RST# VDD_48MHz 48MHz/FS0*
VDD_REF GND_REF X1 X2 VDD_PCI *FS4/PCI0_F *FS3/PCI1 GND_PCI PCI2 PCI3 PCI4 PCI5 PCI6 SDRAMIN *CPU_STOP# *PCI_STOP# *PD# *MULT_SEL GND_48MHz SDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
CPU0 CPU1 VDD_CPU_2.5 VDD_CPU_3.3 CPUT CPUC GND_CPU RST# IREF SDRAM6 GND_SDRAM SDRAM0 SDRAM1 VDD_SDRAM SDRAM2 SDRAM3 GND_SDRAM SDRAM4 SDRAM5 VDD_SDRAM VDD_48MHz 48MHz/FS0* 24_48MHz/FS1* SCLK
CY28317-2
SDRAMIN
7
24_48MHz/FS1* VDD_SDRAM SDRAM0:6
Note: 1. Signals marked with `*' have internal pull-up resistors.
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 20
www.SpectraLinear.com
CY28317-2
Pin Definitions
Pin Name CPU0, CPU1 CPUT, CPUC PCI2:6 PCI1/FS3 Pin No. 48, 47 44, 43 13, 14, 15, 16, 17 11 Pin Type O O O I/O Pin Description CPU Clock Output 0 through 1: CPU clocks for processor and chipset. Differential CPU Clock Output: Differential CPU clocks for processor. PCI Clock Outputs 2 through 6: 3.3V 33-MHz PCI clock outputs. Frequency is set by FS0:4 inputs or through serial data interface. Fixed PCI Clock Output/Frequency Select 3: 3.3V PCI clock outputs. As an output, the frequency is set by FS0:4 inputs or through serial data interface. This pin also serves as a power-on strap option to determine device operating frequency, as described in Table 6. Fixed PCI Clock Output/Frequency Select 4: 3.3V Free-running PCI clock outputs. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 6. Reset# Output: Open drain system reset output.
PCI0_F/FS4
10
I/O
RST#
41
O (open-drai n) I/O
48MHz/FS0
27
48 MHz Output/Frequency Select 0: 3.3V 48-MHz non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 6. 24_48MHz Output/Frequency Select 1: 3.3V 24 or 48 MHz non-spread spectrum output. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 6. Reference Clock Output 1/Frequency Select 2: 3.3V 14.318 MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 6. Reference Clock Output 0: 3.3V 14.318-MHz output clock. SDRAM Buffer Input Pin: Reference input for SDRAM buffer. SDRAM Outputs: These thirteen dedicated outputs provide copies of the signal provided at the SDRAMIN input. Clock pin for SMBus circuitry. Data pin for SMBus circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An output connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Down Control: LVTTL-compatible input that places the device in power-down mode when held LOW. CPU Output Control: 3.3V LVTTL compatible input that stops CPU0, CPU1, CPUT, and CPUC when held LOW. PCI Output Control: 3.3V LVTTL compatible input that stop PCI1:6 when held LOW. Current Reference Input: Current reference for differential CPU output. CPUT and CPUC Output Control: Control the current multiplier for differential CPU output. Set this pin LOW for 1.0V output swing and set this pin HIGH for 0.7V output swing. VTT_PWRGD#: 3.3V LVTTL compatible input that controls the FS0:4 to be latched and enables all outputs. CY28316 will sample the FS0:4 inputs and enable all clock outputs after all the VDD become valid and VTT_PWRGD# is held LOW.
24_48MHz/ FS1 REF1/FS2
26
I/O
2
I/O
REF0 SDRAMIN SDRAM0:6 SCLK SDATA X1
3 18 37, 36, 34, 33, 31, 30, 39 25 24 7
O I O I I/O I
X2 PD# CPU_STOP# PCI_STOP# IREF MULT_SEL
8 21 19 20 40 22
O I I I I I
VTT_PWRGD#
4
I
Rev 1.0, November 25, 2006
Page 2 of 20
CY28317-2
Pin Definitions (continued)
Pin Name VDD_REF, VDD_PCI, VDD_SDRAM, VDD_48MHz VDD_CPU_3.3 VDD_CPU_2.5 GND_REF, GND_PCI, GND_SDRAM, GND_48MHz, GND_CPU Pin No. 5, 9, 28, 29, 35, 45 Pin Type P Pin Description Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect to 3.3V supply.
46 1, 6, 12, 23, 32, 38, 42
P G
Power Connection: Power supply for CPU outputs. Connect to 2.5V supply. Ground Connections: Connect all ground pins to the common system ground plane.
Table 1. Swing Select Functions Mult0 0 1 Board Target Trace/Term Z 60 50 Reference R, IREF= VDD/(3*Rr) Rr = 221 1% IREF = 5.00 mA Rr = 475 1% IREF = 2.32 mA Output Current IOH = 4*IREF IOH = 6*IREF VOH @ Z 1.0V @ 50 0.7V @ 50
Rev 1.0, November 25, 2006
Page 3 of 20
CY28317-2
Serial Data Interface The CY28317-2 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word Write, byte/word Read, block Write and block Read operations from Table 2. Command Code Definition Bit 7 6:0 Descriptions 0 = Block read or block write operation 1 = Byte/Word read or byte/word write operation Byte offset for byte/word read or write operation. For block read or write operations, these bits need to be set at `0000000'. the controller. For block Write/Read operations, the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. For byte/word Write and byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code. The definition for the command code is defined as shown in Table 2.
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 ... ... ... ... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `00000000' stands for block operation Acknowledge from slave Byte count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte N/Slave acknowledge... Data byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 ... ... ... ... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not acknowledge Stop Block Read Protocol Description
Rev 1.0, November 25, 2006
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CY28317-2
Table 4. Word Read and Word Write Protocol Word Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte low - 8 bits Acknowledge from slave Data byte high - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte low from slave - 8 bits Acknowledge Data byte high from slave - 8 bits Not acknowledge Stop Word Read Protocol Description
19 20:27 28 29:36 37 38
19 20 21:27 28 29 30:37 38 39:46 47 48
Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte from slave - 8 bits Not acknowledge Stop Byte Read Protocol Description
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Rev 1.0, November 25, 2006
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CY28317-2
CY28317-2 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 2. All unused register bits (reserved and N/A) should be written to a "0" level. 3. All register bits labeled "Write with 1" must be written to one during initialization.
Byte 0: Control Register 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# - - - - - - - - SEL2 SEL1 SEL0 FS_Override SEL4 SEL3 Spread Select0 Name Spread Select1 Default 0 0 0 0 0 0 0 0 See Table 6 See Table 6 See Table 6 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings See Table 6 See Table 6 `00' = OFF `01' = -0.5% `10' = 0.5% `11' = 0.25% Byte 1: Control Register 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 10 11 2 26 27 48 47 44, 43 Name Latched FS4 input Latched FS3 input Latched FS2 input Latched FS1 input Latched FS0 input CPU0 CPU1 CPUT, CPUC Default X X X X X 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Latched FS[4:0] inputs. These bits are read-only. Description See definition in Bit[0]
Byte 2: Control Register 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3: Control Register 3 Bit Bit 7 Bit 6 Pin# - - Name Reserved SEL_48MHz Default 1 0 Reserved 0 = 24 MHz 1 = 48 MHz Description Pin# 39 10 17 16 15 14 13 11 Name SDRAM6 PCI0_F PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description
Rev 1.0, November 25, 2006
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CY28317-2
Byte 3: Control Register 3 Bit Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 4: Control Register 4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# - - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Pin# 27 26 - 31, 30 34, 33 37, 36 Name 48MHz 24_48MHz Reserved SDRAM4:5 SDRAM2:3 SDRAM0:1 Default 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) Reserved (Active/Inactive) (Active/Inactive) (Active/Inactive) Description
Byte 5: Control Register 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Pin# - - - - Name Reserved Reserved Reserved CPU1 Stop Control Default 0 0 0 0 Reserved Reserved Reserved 0 = CPU1 will be stopped when CPU_STOP# is active 1 = CPU1 will NOT be stopped when CPU_STOP# is active 0 = CPU0 will be stopped when CPU_STOP# is active 1 = CPU0 will NOT be stopped when CPU_STOP# is active 0 = CPUT and CPUC will be stopped when CPU_STOP# is active 1 = CPUT and CPUC will NOT be stopped when CPU_STOP# is active (Active/Inactive) (Active/Inactive) Description
Bit 3
-
CPU0 Stop Control CPUT and CPUC Stop Control REF1 REF0
0
Bit 2
-
0
Bit 1 Bit 0
2 3
1 1
Byte 6: Watchdog Timer Register Bit Bit 7 Bit 6 Name PCI_Skew1 PCI_Skew0 Default 0 0 PCI skew control 00 = Normal 01 = -500 ps 10 = Reserved 11 = +500 ps Pin Description
Rev 1.0, November 25, 2006
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CY28317-2
Byte 6: Watchdog Timer Register (continued) Bit Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name WD_TIMER4 WD_TIMER3 WD_TIMER2 WD_TIMER1 WD_TIMER0 WD_PRE_SC ALER Default 1 1 1 1 1 0 Pin Description These bits store the time-out value of the Watchdog Timer. The scale of the timer is determined by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches "0," it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled. 0 = 150 ms 1 = 2.5 sec
Byte 7: Control Register 7 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# - 25 26 - - - - - Name Reserved 24_48MHz_DRV 48MHz_DRV Reserved Reserved Reserved Reserved Reserved Default 0 1 1 0 0 0 0 0 Reserved 0 = Norm, 1 = High Drive 0 = Norm, 1 = High Drive Reserved Reserved Reserved Reserved Reserved Pin Description
Byte 8: Vendor ID and Revision ID Register (Read Only) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Revision_ID3 Revision_ID2 Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor _ID1 Vendor _ID0 Default 0 0 0 0 1 0 0 0 Revision ID bit[3] Revision ID bit[2] Revision ID bit[1] Revision ID bit[0] Bit[3] of Cypress Semiconductor's Vendor ID. This bit is read-only. Bit[2] of Cypress Semiconductor's Vendor ID. This bit is read-only. Bit[1] of Cypress Semiconductor's Vendor ID. This bit is read-only. Bit[0] of Cypress Semiconductor's Vendor ID. This bit is read-only. Pin Description
Byte 9: System RESET and Watchdog Timer Register Bit Bit 7 Name SDRAM_DRV Default 0 Pin Description SDRAM clock output drive strength 0 = Normal 1 = High Drive PCI clock output drive strength 0 = Normal 1 = High Drive Reserved This bit will enable the generation of a Reset pulse when a Watchdog Timer time-out occurs. 0 = Disabled 1 = Enabled
Bit 6
PCI_DRV
0
Bit 5 Bit 4
Reserved RST_EN_WD
0 0
Rev 1.0, November 25, 2006
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CY28317-2
Byte 9: System RESET and Watchdog Timer Register (continued) Bit Bit 3 Name RST_EN_FC Default 0 Pin Description This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Watchdog Timer Time-out Status bit 0 = No time-out occurs (Read); Ignore (Write) 1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write) 0 = Stop and reload Watchdog Timer. Unlock CY28317-2 from recovery frequency mode. 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Note: CY28317-2 will generate a system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog Timer time-out occurs. Under recovery frequency mode, CY28317-2 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28317-2 from its recovery frequency mode by clearing the WD_EN bit. CPU0:1 clock output drive strength 0 = Normal 1 = High Drive
Bit 2
WD_TO_STATUS
0
Bit 1
WD_EN
0
Bit 0
CPU0:1_DRV
0
Byte 10: Skew Control Register Bit Bit 7 Bit 6 Bit 5 Name CPU0:1_Skew2 CPU0:1_Skew1 CPU0:1_Skew0 Default 0 0 0 CPU 0:1 output skew control 000 = Normal 001 = -150 ps 010 = -300 ps 011 = -450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Reserved Reserved Reserved CPUT and CPUC output skew control 00 = Normal 01 = -150 ps 10 = +150 ps 11 = +300 ps Description
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved Reserved Reserved CPUT&C_Skew1 CPUT&C_Skew0
0 0 0 0 0
Rev 1.0, November 25, 2006
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CY28317-2
Byte 11: Recovery Frequency N-Value Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ROCV_FREQ_N7 ROCV_FREQ_N6 ROCV_FREQ_N5 ROCV_FREQ_N4 ROCV_FREQ_N3 ROCV_FREQ_N2 ROCV_FREQ_N1 ROCV_FREQ_N0 Default 0 0 0 0 0 0 0 0 Pin Description If ROCV_FREQ_SEL is set, CY28317-2 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of the FS_Override bit determines the frequency ratio for CPU and PCI. When it is cleared, CY28317-2 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, CY28317-2 will use the frequency ratio stated in the SEL[4:0] register. CY28317-2 supports programmable CPU frequencies ranging from 50 MHz to 248 MHz. CY28317-2 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] or ROCV_FREQ_M[6:0]. Therefore, it is recommended to use word or block Write to update both registers within the same SMBus bus operation.
Byte 12: Recovery Frequency M-Value Register Bit Bit 7 Name ROCV_FREQ_SEL Default 0 Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] If ROCV_FREQ_SEL is set, CY28317-2 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs. The setting of the FS_Override bit determines the frequency ratio for CPU, SDRAM, and PCI. When it is cleared, CY28317-2 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, CY28317-2 will use the frequency ratio stated in the SEL[4:0] register. CY28317-2 supports programmable CPU frequencies ranging from 50 MHz to 248 MHz. CY28317-2 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] or ROCV_FREQ_M[6:0]. Therefore, it is recommended to use word or block Write to update both registers within the same SMBus bus operation.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ROCV_FREQ_M6 ROCV_FREQ_M5 ROCV_FREQ_M4 ROCV_FREQ_M3 ROCV_FREQ_M2 ROCV_FREQ_M1 ROCV_FREQ_M0
0 0 0 0 0 0 0
Byte 13: Programmable Frequency Select N-Value Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name CPU_FSEL_N7 CPU_FSEL_N6 CPU_FSEL_N5 CPU_FSEL_N4 CPU_FSEL_N3 CPU_FSEL_N2 CPU_FSEL_N1 CPU_FSEL_N0 Default 0 0 0 0 0 0 0 0 Pin Description If Prog_Freq_EN is set, CY28317-2 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of the FS_Override bit determines the frequency ratio for CPU, SDRAM and PCI. When it is cleared, CY28317-2 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, CY28317-2 will use the frequency ratio stated in the SEL[4:0] register. CY28317-2 supports programmable CPU frequencies ranging from 50 MHz to 248 MHz.
Rev 1.0, November 25, 2006
Page 10 of 20
CY28317-2
Byte 14: Programmable Frequency Select M-Value Register Bit Bit 7 Name Pro_Freq_EN Default 0 Description Programmable output frequencies enabled 0 = Disabled 1 = Enabled If Prog_Freq_EN is set, CY28317-2 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of the FS_Override bit determines the frequency ratio for CPU, SDRAM and PCI. When it is cleared, CY28317-2 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, CY28317-2 will use the frequency ratio stated in the SEL[4:0] register. CY28317-2 supports programmable CPU frequencies ranging from 50 MHz to 248 MHz.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPU_FSEL_M6 CPU_FSEL_M5 CPU_FSEL_M4 CPU_FSEL_M3 CPU_FSEL_M2 CPU_FSEL_M1 CPU_FSEL_M0
0 0 0 0 0 0 0
Byte 15: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 16: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Byte 17: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Pin# - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Pin# - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Pin# - - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Vendor test mode Vendor test mode Vendor test mode Default 0 0 0 0 0 0 1 1 Reserved Reserved Reserved Reserved Reserved Reserved. Write with `0' Test mode. Write with `1' Test mode. Write with `1' Description
Rev 1.0, November 25, 2006
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CY28317-2
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions FS4 SEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 200.0 190.0 180.0 170.0 166.0 160.0 150.0 145.0 140.0 136.0 130.0 124.0 67.2 100.8 118.0 134.4 67.0 100.5 115.0 134.0 66.8 100.2 110.0 133.6 105.0 90.0 85.0 78.0 66.6 100.0 75.0 133.3 PCI 33.3 38.0 36.0 34.0 33.2 32.0 37.5 36.3 35.0 34.0 32.5 31.0 33.6 33.6 39.3 33.6 33.5 33.5 38.3 33.5 33.4 33.4 36.7 33.4 35.0 30.0 28.3 39.0 33.3 33.3 37.5 33.3 Output Frequency PLL Gear Constant (G) 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741 48.000741
Rev 1.0, November 25, 2006
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CY28317-2
Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description
The Programmable Output Frequency feature allows users to generate any CPU output frequency in the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. Table 7. Register Summary Name Pro_Freq_EN Description Programmable output frequencies enabled 0 = Disabled (default) 1 = Enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If the FS_Override bit is set, the programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M, and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determine the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use word or block Write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU and PCI. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog Timer time-out occurs The setting of the FS_Override bit determines the frequency ratio for CPU and SDRAM. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] or ROCV_FREQ_M[6:0]. Therefore, it is recommended to use word or block Write to update both registers within the same SMBus bus operation. 0 = Stop and reload Watchdog Timer. Unlock CY28317-2 from recovery frequency mode. 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Note: CY28317-2 will generate system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog Timer time-out occurs. Under recovery frequency mode, CY28317-2 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28317-2 from its recovery frequency mode by clearing the WD_EN bit. Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = Time-out occurred (READ); Clear WD_TO_STATUS (WRITE) The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or gets unstable. System BIOS or other control software can enable the Watchdog Timer before they attempt to make a frequency change. If the system hangs and a Watchdog Timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in Table 7.
FS_Override
CPU_FSEL_N, CPU_FSEL_M
ROCV_FREQ_SEL
ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0]
WD_EN
WD_TO_STATUS
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CY28317-2
Table 7. Register Summary (continued) Name WD_TIMER[4:0] Description These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches "0," it will set the WD_TO_STATUS bit. 0 = 150 ms 1 = 2.5 sec This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled "G" stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 4. The ratio of (N+3) and (M+3) need to be greater than "1" [(N+3)/(M+3) > 1]. The following table lists set of N and M values for different frequency output ranges.This example uses a fixed value for the M-Value register and selects the CPU output frequency by changing the value of the N-Value register.
WD_PRE_SCALER RST_EN_WD
RST_EN_FC
How to Program CPU Output Frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3) "N" and "M" are the values programmed in Programmable Frequency Select N-Value register and M-Value register, respectively.
Table 8. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges 50 MHz - 129 MHz 130 MHz - 248 MHz Gear Constants 48.00741 48.00741 Fixed Value for M-Value Register 93 45 Range of N-Value Register for Different CPU Frequency 97-255 127-245
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CY28317-2
Absolute Maximum Ratings[2]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Parameter VDD, VIN TSTG TB TA ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min.) Unit V C C C kV
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V 5%[3]
Parameter Supply Current IDD3 3.3V Supply Current VDD = 3.465V, FCPU = 133 MHz IDDPD3 Logic Inputs VIL VIH IIL IIH VOL VOH IOL Input Low Voltage Input High Voltage Input Low Current[4] Input High Current[4] Output Low Voltage Output High Voltage Output Low Current PCI0:5 REF0:1 48 MHz 24 MHz SDRAM IOH Output High Current PCI0:5 REF0:1 48 MHz 24 MHz SDRAM IOL = 1 mA IOH = -1 mA VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOL = 1.5V VOH = 1.5V VOH = 1.5V VOH = 1.5V VOH = 1.5V VOH = 1.5V 3.1 70 50 50 50 70 70 50 50 50 70 110 70 70 70 110 110 70 70 70 110 135 100 100 100 135 135 100 100 100 135 GND - 0.3 2.0 0.8 VDD + 0.3 -25 10 50 V V A A mV V mA mA mA mA mA mA mA mA mA mA 3.3V Shut down Current VDD = 3.465V 25 mA 250 mA Description Test Condition Min. Typ. Max. Unit
Clock Outputs
Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. transmission lines with 20-pF capacitors. 3. All clock outputs loaded with 6" 60 4. CY28317-2 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
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CY28317-2
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V 5%[3] (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[5] Load Capacitance, Imposed on External Crystal[6] X1 Input Capacitance[7] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDDQ3 = 3.3V 1.65 18 TBD 5 6 7 V pF pF pF pF nH Description Test Condition Min. Typ. Max. Unit
Pin Capacitance/Inductance
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. CPU Clock Outputs[8] CPU = 100 MHz Parameter tR tF tD tJC fST Description Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle to Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. VO = VX 3 Measured at 50% point Test Condition/Comments Min. 1.0 1.0 45 Typ. Max. 4.0 2.0 55 250 3 CPU = 133 MHz Min. 1.0 1.0 45 Typ. Max. 4.0 2.0 55 250 Unit v/ns v/ns % ps ms
Zo
50
50
Notes: 5. X1 input threshold voltage (typical) is VDD/2. 6. The CY28317-2 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. The total load placed on the crystal is 18 pF; this includes typical stray capacitance of short PCB traces to the crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 8. Determined as a fraction of 2* (tRP - tRN). Where tRP is a rising edge and tRN is an intersection falling edge.
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CY28317-2
PCI Clock Outputs, PCI (Lump Capacitance Test Load = 20 pF) Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on the rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on the rising and falling edges at 1.5V Measured on the rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on the rising edge at 1.5V Covers all CPU/PCI outputs. Measured on the rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 30 1.5 Min. 30 12 12 1 1 45 4 4 55 250 500 4 3 Typ. Max. Unit ns ns ns V/ns V/ns % ps ps ns ms
Zo
REF Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on the rising and falling edges at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on the rising and falling edges at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
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CY28317-2
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 24 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (24.004 - 24)/24 (14.31818 MHz x 57/34 = 24.004 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on the rising and falling edges at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 24.004 +167 57/34 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
Ordering Information
Ordering Code CY28317PVC-2 CY28317PVC-2T CY28317ZC-2 CY28317ZC-2T 48-pin SSOP 48-pin SSOP - Tape and Reel 48-pin TSSOP 48-pin TSSOP - Tape and Reel Package Type Operating Range Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C
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CY28317-2
Layout Diagram
+3.3V Supply FB
VDDQ3
0.005 F 10 F
+2.5V Supply FB
VDDQ2
C4 G G
C3
C4
0.005 F
10 F
C3
G
G
G
G
1G 2 3G 4 5V 6 7 8G 9V 10 G 11 12 13 G 14 15 G 16 17 18 G 19 20 G 21 22 G 23 24 G
G
48 47 V 46 V 45 G 44 G 43 42 G 41 40 39 G 38 37 G 36 V 35 34 G 33 32 G 31 30 V 29 V 28 G 27 26 G 25
G
G G
G
FB = Dale ILB1206 - 300 (300 @ 100 MHz) or TDK ACB2012L-120 Ceramic Caps C3 = 10-22 F C4 = 0.005 F C6 = 0.01 F G = VIA to GND plane layer V = VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
CY28317-2
G
G G
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CY28317-2
Package Drawing and Dimension
48-Lead Shrunk Small Outline Package O48
48-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 25, 2006
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